Function core::arch::mips64::__msa_srlri_w

pub unsafe fn __msa_srlri_w<const IMM5: i32>(a: v4i32) -> v4i32

🔬 This is a nightly-only experimental API. (stdsimd #48556)

This is supported on MIPS-64 and target feature msa only.

Immediate Shift Right Logical Rounded

The elements in vector a (four signed 32-bit integer numbers) are shifted right logical by imm6 bits.The most significant discarded bit is added to the shifted value (for rounding) and the result is written to vector (four signed 32-bit integer numbers).